Informatics Publishing Limited

Bairu K. Saptalakar ¹, Deepak Kale ¹, Mahesh Rachannavar ¹, M. K. Pavankumar ¹

Affiliations
1 Department of Electronics and Communication Engineering, Shri Dharmasthala Manjunatheshwara College of Engineering and Technology, Dharwad, Karnataka, IN

Abstract

Multiplication is most commonly used operation in mathematics. Integer multiplication is used commonly in the real world, binary multiplication is the basic multiplication used for the integer multiplication. Systolic algorithms are the efficient algorithms to perform the binary multiplication [1]. Systolic array is an arrangement of processors in an array where data flows synchronously across the array between neighbors, usually with different data flowing in different directions. Each processor at each step takes in data from one or more neighbors (e.g. North and West), processes it and, in the next step, outputs results in the opposite direction (South and East) [2]. The present work is concentrated on developing hardware model for systolic multiplier using VHDL (Very High Speed Integrated Circuits Hardware Description Language) as a platform. The design is simulated using modelsim simulator and synthesized on Spartan 3 FPGA board.

Keywords

Systolic Array, Parallel Processing, Xilinx, FPGA, VHDL.

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